Patent Document 1 discloses one example of the arrangement of a digital driver which is used in a display device. FIG. 9 illustrates the arrangement. The digital driver illustrated in FIG. 9 includes, for each data signal line (S1, . . . ) of a display panel, a circuit block including a plurality of first (1st) latch circuits LAT1 and a plurality of second (2nd) latch circuits LAT2.
In this arrangement, each of the circuit blocks acquires, from D0 through D2, 3-bit data to be supplied to one corresponding data signal line, in response to a pulse signal (1st latch pulse signal) transmitted from a corresponding DEF in a shift register. Then, each of the circuit blocks carries out DA conversion on the 3-bit data in response to a pulse signal (2nd latch pulse signal) transmitted from an LP line, and outputs, to a corresponding one of the data signal lines (S1, S2, . . . ), an analog signal potential thus obtained.
Also, Patent Document 1 discloses another example of the arrangement of a digital driver. FIG. 10 illustrates the arrangement. A digital driver illustrated in FIG. 10 includes, for each group of four digital signal lines (S1 to S4, S5 to S8, . . . ) of a display panel, a circuit block including a plurality of first (1st) latch circuits LAT1 and a plurality of second (2nd) latch circuits LAT2.
In this arrangement, one horizontal period (a period constituted by the first period to the fourth period) is divided into four, and one circuit block is shared with the four data signal lines.
In the first period, each of the circuit blocks acquires, from D0 through D2, 3-bit data to be supplied to a corresponding one of the data signal line (S1, S5, . . . ), in response to a pulse signal (1st latch pulse signal) transmitted from a corresponding DEF in a shift register. Then, each of the circuit blocks carries out DA conversion on the 3-bit data in response to a pulse signal (2nd latch pulse signal) transmitted from an LPa line or an LPb line, and outputs, to a corresponding one of the data signal lines (S1, S5, . . . ), an analog signal potential thus obtained. In the second period which starts subsequently, each of the circuit blocks acquires, from D0 through D2, 3-bit data to be supplied to a corresponding one of the data signal lines (S2, S3, . . . ), in response to a pulse signal (1st latch pulse signal) transmitted from the corresponding DEF in the shift register. Then, each of the circuit blocks carries out DA conversion on the 3-bit data in response to a pulse signal (2nd latch pulse signal) transmitted from the LPa line or the LPb line, and outputs, to a corresponding one of the data signal lines (S2, S6, . . . ), an analog signal potential thus obtained. In the third period and the fourth period, this process is carried out in a similar manner.
[Patent Document 1]
Japanese Unexamined Patent Application Publication, Tokukai, No. 2003-58133 (published on Feb. 28, 2003)